This invention is an improved sample-and-hold circuit.
A sample-and-hold circuit is commonly used to "hold" at its output for a predetermined time the voltage that was applied to its input during a short "sampling" period, usually during that time immediately prior to the holding period. Commonly, a variable voltage is applied to the input, a pulse is applied to initiate a sampling period, and the output will continue for some period to output the input voltage level that existed at the time of the pulse. A problem inherent in this type of circuit is that the sampling pulse is coupled through to the output line, which impairs the accuracy of the circuit. More specifically, in an uncompensated sample-and-hold circuit, during the sampling period the output voltage is an accurate representation of the input voltage, but, at the end of that period, the trailing edge of the sampling pulse is coupled through the gate-to-drain capacitance to the output, resulting in a dc offset or "hold step". This is especially true in high speed circuits. A complex and necessarily expensive circuit could be designed to minimize this effect. What is required is a simple circuit that would accomplish this result.